-- 7人表决器，半数以上为1，以下为0，并把为1的数量用7段数码管显示出来
------------------------------


library ieee;
use ieee.std_logic_1164.all;

entity judge7 is
    port(
        v0, v1, v2, v3, v4, v5, v6 : in std_logic;
        do : out std_logic,
        a, b, c, d, e, f, g : out std_logic
    );
end entity;

architecture behave of judge7 is

    signal v, y : std_logic_vector(6 downto 0);
    signal count : std_logic_vector(3 downto 0);

begin

    v <= v0 & v1 & v2 & v3 & v4 & v5 & v6;

    process(v) 
        variable m : std_logic_vector(3 downto 0);
    begin
        m := "0000";
        for i in 6 downto 0 loop
            if v(i) = '1' then m := m + 1;
            end if;
        end loop;

        count <= m;
        
        if m = "0100" or m = "0101" or m = "0110" or m = "0111" then do = '1';
        then d = '0';
        end if;        
    end process;
    
    process(count) begin
        case count is
            when "0000" => y <= "1111110";
            ...
        end case;        
    end process;

    a <= y(6);
    b <= y(5);
    c <= y(4);
    d <= y(3);
    e <= y(2);
    f <= y(1);
    g <= y(0);

end behave;